The inventive concepts relate to semiconductor circuits including digital-to-time converter (DTC) circuits, and more particularly, to phase locked loop circuits, clock signal generator including DTC circuits, a methods of operating the phase locked loop circuits and the clock signal generators, and wireless communication devices.
A DTC generates delayed clock signals by delaying reference clock signals that are input according to received digital codes. The DTC may be used in an oscilloscope, a fractional-N phase locked loop (PLL), a time interleaved analog-to-digital converter (ADC), or the like. A DTC included in the fractional-N PLL circuit may delay in advance, a reference clock signal, by as much as a delay amount corresponding to a quantization error and provide the delayed reference clock signal as an input clock of a phase locked loop, and thus a quantization error of the fractional-N PLL circuit may be removed in advance. For the effective operation of the DTC, it is desirable to quickly derive a gain value of the DTC that satisfies operation conditions of a clock signal generator including the DTC.